ANALOG AND DIGITAL ELECTRONICS LABORATORY (18CSL37)

ANALOG AND DIGITAL ELECTRONICS 

LABORATORY 

Subject Code:18CSL37

CIE Marks:40

SEE Marks:60

Number of Contact Hours/Week:0:2:2

Total Number of Lab Contact Hours:36

Exam Hours:3 

HrsCredits – 2

Course Learning Objectives: This course (18CSL37) will enable students to:

This laboratory course enables students to get practical experience in design, assembly and evaluation/testing of
• Analog components and circuits including Operational Amplifier, Timer, etc.
• Combinational logic circuits.
• Flip - Flops and their operations
• Counters and registers using flip-flops.
• Synchronous and Asynchronous sequential circuits.
 • A/D and D/A converters
Descriptions (if any):
• Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant.
• For Part A (Analog Electronic Circuits) students must trace the waveform on the Tracing sheet / Graph sheet and label trace.
• Continuous evaluation by the faculty must be carried by including a performance of a student in both hardware implementation and simulation (if any) for the given circuit.
• A batch not exceeding 4 must be formed for conducting the experiment. For simulation individual student must execute the program.

Laboratory Programs:

PART A (Analog Electronic Circuits)
1. Design an astable multivibrator ciruit for three cases of duty cycle (50%, <50% and >50%) using NE 555 timer IC. Simulate the same for any one duty cycle.


2. Using appropriate linear IC regulators, design fixed +5V and -12V regulator circuits. For the rectification design a full wave bridge rectifier ciruit. And simulate the same.


3. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And simulate the same.


4. Using ua 741 opamap, design a window comparate for any given UTP and LTP. And simulate the same.


5. Demonstrate the use of LED and photodiode for an alarm system.

PART B (Digital Electronic Circuits)

6. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic gates. And implement the same in HDL.


7. Given a 4-variable logic expression, simplify it using appropriate technique and realize the simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.


8. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And implement the same in HDL.


9. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and demonstrate its working.


10. Design and implement an asynchronous counter using decade counter IC to count up from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447)

Laboratory Outcomes: The student should be able to:

• Use appropriate design equations / methods to design the given circuit.
• Examine and verify the design of both analog and digital circuits using simulators.
• Make us of electronic components, ICs, instruments and tools for design and testing of circuits for the given the appropriate inputs.
• Compile a laboratory journal which includes; aim, tool/instruments/software/components used, design equations used and designs, schematics, program listing, procedure followed, relevant theory, results as graphs and tables, interpreting and concluding the findings.
Conduct of Practical Examination:
• All laboratory experiments, excluding the first, are to be included for practical examination. • Experiment distribution
o For questions having only one part: Students are allowed to pick one experiment from the lot and are given equal opportunity.
o For questions having part A and B: Students are allowed to pick one experiment from part A and one experiment from part B and are given equal opportunity.
• Change of experiment is allowed only once and marks allotted for procedure part to be made zero.
• Marks Distribution (Subjected to change in accoradance with university regulations)
a) For questions having only one part – Procedure + Execution + Viva-Voce: 15+70+15 = 100 Marks
b) For questions having part A and B
i. Part A – Procedure + Execution + Viva = 4 + 21 + 5 = 30 Marks ii. Part B – Procedure + Execution + Viva = 10 + 49+ 11 = 70 Marks

LAB Manual: