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Verilog HDL(18EC56)

Verilog HDL

Course Code:18EC56
 IA Marks:40
Exam Marks:60
Number of Lecture Hours/Week:03
Total Number of Lecture Hours:40 (08 Hours per Module)
Exam Hours:03

Course Learning Objectives:

• Learn different Verilog HDL constructs.
• Familiarize the different levels of abstraction in Verilog.
• Understand Verilog Tasks, Functions and Directives.
• Understand timing and delay Simulation.
• Understand the concept of logic synthesis and its impact in verification

Module 1

Overview of Digital Design with Verilog HDL: Evolution of CAD, emergence of HDLs,
typical HDL-flow, why Verilog HDL?, trends in HDLs.
Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences
between modules and module instances, parts of a simulation, design block, stimulus block.

Click here to download Module-1

Module 2

Basic Concepts: Lexical conventions, data types, system tasks, compiler directives.
Modules and Ports: Module definition, port declaration, connecting ports, hierarchical name

Module 3

Gate-Level Modeling: Modeling using basic Verilog gate primitives, description of and/or and
buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays.
Dataflow Modeling: Continuous assignments, delay specification, expressions, operators, operands,
operator types.

Module 4

Behavioral Modeling: Structured procedures, initial and always, blocking and non-blocking
statements, delay control, generate statement, event control, conditional statements, Multiway
branching, loops, sequential and parallel blocks.
Tasks and Functions: Differences between tasks and functions, declaration, invocation, automatic
tasks and functions.

Module 5

Useful Modeling Techniques: Procedural continuous assignments, overriding parameters,
conditional compilation and execution, useful system tasks.
Logic Synthesis with Verilog: Logic Synthesis, Impact of logic synthesis, Verilog HDL
Synthesis, Synthesis design flow, Verification of Gate-Level Netlist. (Chapter 14 till 14.5 of

• Write Verilog programs in the gate, dataflow (RTL), behavioral and switch modeling levels of Abstraction.

Important Links:

1. click here to download Question Bank

3. click here to download Previous Year Question Papers

 (refer PYQ from Module-1 to Module-4 only)

4. click here to download full notes

Note: TextBook links are given below

Course Outcomes: At the end of this course, students should be able to

• Design and verify the functionality of digital circuit/system using test benches.

• Identify the suitable Abstraction level for a particular digital design.

• Write the programs more effectively using Verilog tasks, functions and directives.

• Perform timing and delay Simulation

• Interpret the various constructs in logic synthesis.

Question paper pattern:

• Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks.

• Each full question can have a maximum of 4 sub questions.

• There will be 2 full questions from each module covering all the topics of the module.

• Students will have to answer 5 full questions, selecting one full question from each module.

• The total marks will be proportionally reduced to 60 marks as SEE marks is 60.

Text Book:

Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson Education, Second Edition.

Reference Books:

1. Donald E. Thomas, Philip R. Moorby, “The Verilog Hardware Description Language”, Springer Science+Business Media, LLC, Fifth edition.

2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson (Prentice Hall), Second edition.

3. Padmanabhan, Tripura Sundari, “Design through Verilog HDL”, Wiley, 2016 or earlier.

Softcopy Textbook Links:

1. Verilog HDL: A Guide to Digital Design and Synthesis”,Samir Palnitkar, Download/View

2. Advanced Digital Design with the Verilog HDL Michael D. Ciletti, Download/View

3. The Verilog Hardware Description Language Donald E. Thomas, Philip R. Moorby,  Download/View

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