BASIC VLSI DESIGN (18EC655)

BASIC VLSI DESIGN

• Course Code 18EC655 
• CIE Marks 40
• Number of Lecture Hours/Week 03 
• SEE Marks 60
• Total Number of Lecture Hours 40(8Hours/Module) 
• Exam Hours 03
• CREDITS – 03

Course objective: This course will enable students to:

• Understand the fundamental aspects of circuits in silicon
• Relate to VLSI design processes and design rules

Module-1

Moore’s law, speed power performance, nMOS fabrication, CMOS fabrication: n-well, well processes, BiCMOS, Comparison of bipolar and CMOS. Basic Electrical Properties of MOS And BiCMOS Circuits: Drain to source current versus voltage characteristics, threshold voltage, transconductance.

Module-2

Basic Electrical Properties of MOS And BiCMOS Circuits: nMOS inverter, Determination of pull up to pull down ratio: nMOS inverter driven through one or more pass transistors, alternative forms of pull up, CMOS inverter, BiCMOS inverters, latch up. Basic Circuit Concepts: Sheet resistance, area capacitance calculation, Delay unit, inverter delay, estimation of CMOS inverter delay, super buffers, BiCMOS drivers.

Module-3

MOS and BiCMOS Circuit Design Processes: MOS layers, stick diagrams, nMOS design style, CMOS design style Design rules and layout & Scaling of MOS Circuits: λ - based design rules, scaling factors for device parameters

Module-4

Subsystem Design and Layout-1: Switch logic pass transistor, Gate logic inverter, NAND gates, NOR gates, pseudo nMOS, Dynamic CMOS Examples of structured design: Parity generator, Bus arbitration, multiplexers, logic function block, code converter.

Module-5

Subsystem Design and Layout-2: Clocked sequential circuits, dynamic shift registers, bus lines, General considerations, 4-bit arithmetic processes, 4-bit shifter, Regularity- Definition & Computation Practical aspects and testability: Some thoughts of performance, optimization and CAD tools for design and simulation.

Course Outcomes: After studying this course, students will be able to:

1. Identify the CMOS layout levels, and the design layers used in the process sequence.
2. Describe the general steps required for processing of CMOS integrated circuits.
3. Design static CMOS combinational and sequential logic at the transistor level.
4. Demonstrate different logic styles such as complementary CMOS logic, pass-transistor Logic,
dynamic logic, etc.
5. Interpret the need for testability and testing methods in VLSI.

Question paper pattern:

• Examination will be conducted for 100 marks with question paper containing 10 full
questions, each of 20 marks.
• Each full question can have a maximum of 4 sub questions.
• There will be 2 full questions from each module covering all the topics of the module.
• Students will have to answer 5 full questions, selecting one full question from each module.
• The total marks will be proportionally reduced to 60 marks as SEE marks is 60.

Text Books:

“Basic VLSI Design”, Douglas A Pucknell, Kamran Eshraghian, 3rd Edition, Prentice Hall
of India publication, 2005.

References:

1. “CMOS Digital Integrated Circuits, Analysis And Design”, Sung – Mo (Steve) Kang, Yusuf Leblebici, Tata McGraw Hill, 3rd Edition, 2003.
2. “VLSI Technology”, S.M. Sze, 2nd edition, Tata McGraw Hill, 2003.