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LD (Logic Design) Lab using Pspice / MultiSIM (21EC381)

LD (Logic Design) Lab using Pspice / MultiSIM

Course Code:21EC381 
CIE Marks:50
Teaching Hours/Week (L: T:P: S):0:0:2:0 
SEE Marks:50
Exam Hours:03


1 Implementation of De Morgan’s theorem and SOP/POS expressions using Pspice/Multisim.

2 Implementation of Half Adder, Full Adder, Half Subtractor and Full Subtractor using Pspice/ Multisim.

3 Design and implementation of 4-bit Parallel Adder/ Subtractor using IC 7483 and BCD to Excess-3 code conversion and vice-versa using Pspice/Multisim.

4 Design and implement of IC 7485 5-bit magnitude comparator using Pspice/Multisim.

5 To Realize Adder & Subtractor using IC 74153 (4:1 MUX) and 4-variable function using IC74151 (8:1MUX) using Pspice/Multisim.

6 To realize Adder and Subtractor using IC 74139/ 74155N (Demux/Decoder) and Binary to Gray code conversion & vice versa using 74139/ 74155N using Pspice/Multisim.

7 SR, Master-Slave JK, D & T flip-flops using NAND Gates using Pspice/Multisim.

8 Design and realize the Synchronous counters (up/down decade/binary) using Pspice/Multisim.

9 Realize the shift registers and their modes (SISO, PISO, PIPO, SIPO) using 7474/7495 using Pspice/Multisim.

10 Design Pseudo Random Sequence generator using 7495 using Pspice/Multisim.

11 Design Serial Adder with Accumulator and simulate using Pspice/Multisim.

12 Design using Pspice/Multisim Mod-N Counters.

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