Digital Design and Computer Organization (BCS302)

Digital Design and Computer Organization

Course Code BCS302 
CIE Marks 50 Teaching Hours/Week (L:T:P: S) 3:0:2:0 
SEE Marks 50 
Total Hours of Pedagogy 40 hours Theory + 20 Hours of Practicals 
Total Marks 100 
Credits 04 
Exam Hours 3 
Examination nature (SEE) Theory 

 MODULE-1 

Introduction to Digital Design: Binary Logic, Basic Theorems And Properties Of Boolean Algebra, Boolean Functions, Digital Logic Gates, Introduction, The Map Method, Four-Variable Map, Don’t-Care Conditions, NAND and NOR Implementation, Other Hardware Description Language – Verilog Model of a simple circuit. Text book 1: 1.9, 2.4, 2.5, 2.8, 3.1, 3.2, 3.3, 3.5, 3.6, 3.9 

MODULE-2 

Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary Adder- Subtractor, Decoders, Encoders, Multiplexers. HDL Models of Combinational Circuits – Adder, Multiplexer, Encoder. Sequential Logic: Introduction, Sequential Circuits, Storage Elements: Latches, Flip-Flops. Text book 1: 4.1, 4.2, 4.4, 4.5, 4.9, 4.10, 4.11, 4.12, 5.1, 5.2, 5.3, 5.4. 

MODULE-3 

Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus structure, Performance – Processor Clock, Basic Performance Equation, Clock Rate, Performance Measurement.Machine Instructions and Programs: Memory Location and Addresses, Memory Operations, Instruction and Instruction sequencing, Addressing Modes. Text book 2: 1.2, 1.3, 1.4, 1.6, 2.2, 2.3, 2.4, 2.5 

MODULE-4 

Input/output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and Disabling Interrupts, Handling Multiple Devices, Direct Memory Access: Bus Arbitration, Speed, size and Cost of memory systems. Cache Memories – Mapping Functions. Text book 2: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4, 5.4, 5.5.1 

MODULE-5

Basic Processing Unit: Some Fundamental Concepts: Register Transfers, Performing ALU operations, fetching a word from Memory, Storing a word in memory. Execution of a Complete Instruction. Pipelining: Basic concepts, Role of Cache memory, Pipeline Performance. Text book 2: 7.1, 7.2, 8.1

 PRACTICAL COMPONENT OF IPCC 

Sl.N O Experiments Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant 1 Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same using basic gates. 

2 Design a 4 bit full adder and subtractor and simulate the same using basic gates. 

3 Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioural model. 4 Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and Full Subtractor. 

5 Design Verilog HDL to implement Decimal adder. 

6 Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1. 

7 Design Verilog program to implement types of De-Multiplexer. 8 Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D. 

Suggested Learning Resources: Books 

1. M. Morris Mano & Michael D. Ciletti, Digital Design With an Introduction to Verilog Design, 5e, Pearson Education. 

2. Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer Organization, 5 th Edition, Tata McGraw Hill.