Digital System Design using Verilog (BEC654A)

Digital System Design using Verilog

Course Code BEC654A 
CIE Marks 50
Teaching Hours/Week(L:T:P) 3:0:0 
SEE Marks 50
Total Hours of Pedagogy 40 
Total Marks 100
Credits 03 
Exam Hours 3
Examination type (SEE) Theory

 

Module-1

Overview of Digital Design with Verilog HDL: Evolution of Computer-Aided Digital Design (CAD), Emergence of HDLs, Typical Design flow, Importance of HDLs, Popularity of Verilog HDL, Trends in HDLs. 

Hierarchical Modeling Concepts: Design Methodologies, Top-down and Bottom-up design methodology, Modules, Instances, Components of a Simulation, Design Block, Stimulus Block (Test Bench) with example. 

Module-2

Basic Concepts: Lexical Conventions, Data Types, System Tasks, Compiler Directives.

Modules and Ports: Modules, Ports, Connecting Ports, Hierarchical Names. 

Module-3

Gate-Level Modeling: Gate Types-Modeling using basic Verilog gate primitives, Description of AND/OR and BUF/NOT type gates. Gate Delays-Rise, Fall and Turn-Off Delays, Min, Max and Typical Delays.

Dataflow Modeling: Continuous assignments, Delay Specification, Expressions, Operators, Operands, Operator Types, 

Module-4

Behavioral Description: Structured Procedures, Initial and Always statements, Procedural Assignments Blocking and Non-Blocking statements, Conditional statements, Multiway Branching, Loops, Sequential and Parallel blocks, Examples-4-to-1 Multiplexer, 4-bit Counter.

Module-5

Structural Description: Highlights of Structural Descriptions, Organization of Structural Description, Binding 

Tasks and Functions: Differences between Tasks and Functions, Declaration and Invocation, 

Suggested Learning Resources:

Text Books:

1. “Verilog HDL: A Guide to Digital Design and Synthesis”, Samir Palnitkar, Pearson education,  Second edition.

2. “HDL programming (VHDL and Verilog)”, Nazeih M Botros, John Wiley India Pvt. Ltd., 2008.

Reference Books:

1. Donald E. Thomas, Philip R. Moorby, “The Verilog Hardware Description Language”, Springer Science+Business Media, LLC, Fifth edition.

2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson (Prentice Hall), Second edition.

3. Padmanabhan, Tripura Sundari, “Design through Verilog HDL”, Wiley, 2016 or earlier