FPGA Based System design Lab Using Verilog (BECL657A)

FPGA Based System design Lab Using Verilog

Course Code BECL657A
CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2:0 
SEE Marks 50
Credits 01 
Exam Hours 3
Examination type (SEE) Practical

1 Write a Verilog description for the following combinational logic, Verify the design using Verilog test bench and perform the synthesis by downloading the design on to FPGA device.

a. Structural modelling of Full adder using two half adders and or Gate

b. BCD to Excess-3 code converter

2 Write a Verilog description for the following Sequential Circuits,Verify the design using Verilog test bench and perform the synthesis by downloading the design on to FPGA device.

a. Mod-N counter

b. Random sequence counter

3 Write a Verilog description for the following Sequential Circuits, Verify the design using Verilog test bench and perform the synthesis by downloading the design on to FPGA device.

a. SISO and PISO shift register

b. Ring counter

4 Write a Verilog description for the following Digital Circuits, Verify the functionality usingVerilog test bench and perform the synthesis by downloading the design on to FPGA device.

a.4-Bit Ripple Carry Adder

b. 4-Bit Linear Feedback shift register

5 Write a Verilog description for the following Digital Circuits, Verify the functionality using Verilog test bench and perform the synthesis by downloading the design on to FPGA device.

 a. 4-bitArray Multiplication

 b. 4-bit Booth Multiplication

6 Write a Verilog description to design a clock divider circuit that generates 1/2, 1/3rdand 1/4thclock from a given input clock. Port the design to FPGA and validate the functionality using output device.

7 Interface a Stepper motor to FPGA andWrite a Verilog description to controlStepper motor rotation.

8 Interface a DAC to FPGA and Write a Verilog descriptionto generate Squre wave of frequency F KHz. Modify the code to down sample the frequency to F/2 KHz. Display the original and Down sampled signals by connecting them to an output device.

9 Write a Verilog descriptionto convert an analog input of a sensor to digital form and to display the same on a suitable display like set of simple LEDs like 7-Segment display digits.

Suggested Learning Resources:

1) SamirPalnitkar, “Verilog HDL : A guide to digital design and synthesis”, Pearson Education, II Edition. Templatefor Practical Course and if AEC is a practical Course Annexure-V

2) Donald E Thomas, Philip R Moorby, “The Verilog hardware description Language”, Springer Science Business Media , LLC, 5th Edition

3) Michael D. Ciletti, “Advanced digital design with the Verilog HDL”, Pearson (PHI),II Edition