VLSI Design and Testing LAB (BECL606)

VLSI Design and Testing LAB

Course Code BECL606 
CIE Marks 50
Teaching Hours/Week (L: T: P: S) 0:0:2:0 
SEE Marks 50
Credits 1 
Exam Hours 3

Experiments

1 Design a 4-Bit Adder

• Write a Verilog description

• Verify the Functionality using Test-bench

• Synthesize the design by setting proper constraints and generate the gate level netlist. 

From the report generated identify Critical path, Maximum delay, Total number of cells, Power requirement and Total area required

2 4-Bit Shift and add Multiplier

• Write Verilog Code

• Verify the Functionality using Test-bench

• Synthesize the design by setting proper constraints and obtain the gate level netlist.

From the report generated identify Critical path, Maximum delay, Total number of cells, Power requirement and Total area required

3 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for ALU Behavioral Modeling

• Write Verilog description

• Verify functionality using Test-bench

• Synthesize the design targeting suitable library and by setting area and timing constraints

• Tabulate the Area, Power and Delay for the Synthesized netlist

• Identify Critical path

4 Flip-Flops ( D,SR and JK )

• Write the Verilog description

• Verify the Functionality using Test-bench

• Synthesize the design by setting proper constraints and obtain the gate level netlist.

From the report gate level netlist identify Critical path, Maximum delay, Total number of cells, Power requirement and Total area required.

• Verify the functionality using Gate level netlist and compare the results at RTL and gate level netlist.

5 Four bit Synchronous MOD-N counter with Asynchronous reset

• Write Verilog Code

• Verify functionality using Test-bench

• Synthesize the design targeting suitable library and by setting area and timing constraints

• Tabulate the Area, Power and Delay for the Synthesized netlist Identify Critical path

• Verify the functionality using Gate level netlist and compare the results at RTL and gate level netlist.

6 a) Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology. Carry out the following:

i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and the time period of 20ns and plot the input voltage and output voltage of designed inverter?

ii. From the simulation result compute tpHL, tpLH and td for all three geometrical settings of width?

iii. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter.

b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post layout simulations, compare the results with pre layout simulations and compare the results.

7 Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS inverter computed in experiment above. Verify the functionality of NOR gate and also find out the delay td for all four possible combinations of input vectors. Table the results. Increase the drive strength to 2X and 4X and tabulate the results.

 8 Construct the schematic of the Boolean Expression

 Y= AB+CD+E using CMOS Logic. Verify the functionality of the expression find out the delay td for some combination of input vectors. Tabulate the results.

9 a) Construct the schematic of Common Source Amplifier with PMOS Current Mirror Load and find its transient response and AC response? Measure the Unit Gain Bandwidth (UGB), amplification factor by varying transistor geometries, study the impact of variation in width to UGB.

 b) Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC & LVS, extract parasitic and perform post layout simulations, compare the results with prelayout simulations. Record the observations.

10 a) Construct the schematic of two-stage operational amplifier and measure the following:

 i. Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase margin with and without coupling capacitance iv. Use the op-amp in the inverting and non-inverting configuration and verify its functionality. v. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the stage wise transistor geometries and record the observations.

b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in 180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained in part a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout simulations and perform the comparative analysis.

Demonstration Experiments ( For CIE )

11 UART

• Write Verilog description

• Verify the Functionality using Test-bench

• Synthesize the design targeting suitable library and by setting area and timing constraints

• Tabulate the Area, Power and Delay for the Synthesized netlist, Identify Critical path

12 Design and characterize 6T binary SRAM cell and measure the following:

• Read Time, Write Time, SNM, Power

• Draw Layout of 6T SRAM, use optimum layout methods. Verify for DRC & LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout simulations. Record the observations.