DIGITAL SYSTEMS DESIGN USING VHDL (18EC754)

DIGITAL SYSTEMS DESIGN USING VHDL

Course Code 18EC754 
CIE Marks 40
Number of Lecture Hours/Week 03 
SEE Marks 60
Total Number of Lecture Hours 40(8Hours/Module) 
Exam Hours 03
CREDITS – 03

Course objective: This course will enable students to:

• Use the industry-standard hardware description language VHDL into the digital design process.
• Design VHDL models ranging in complexity from a simple adder to more complex circuits.
• Understand the synthesis and testing of the models.

Module-1

Review of Logic Design Fundamentals: Combinational logic, Boolean Algebra and Algebraic Simplification, Karnaugh maps, Designing with NAND and NOR gates, Hazards in combinational Networks, Flipflop and Latches, Mealy Sequential Network Design, Design of Moore Sequential Network, Equivalent states and reduction of state Tables, Synchronous Design, Tristate Logic and
Buses (Text 1, Chapter 1- 1.1 to 1.9, 1.12, 1.13) L1, L2, L3

Module-2

Introduction to VHDL: VHDL Description of Combinational Networks, Modeling Flipflops
using VHDL Processes, VHDL Models for a Multiplexer, Modeling a sequential Machine, Variables, signals, and constants, Arrays, VHDL operators, VHDL Functions, VHDL Procedures, Packages and Libraries. (Text 1, Chapter 2- 2.1, 2.2, 2.3, 2.5, 2.6, 2.7, 2.8, 2.9, 2.10, 2.11) L1, L2, L3

Module-3

Styles of Descriptions: VHDL Data types, VHDL Styles of Description (Text 2, Chapter 1- 1.5, 1.6)
Data flow Description: Highlights of Data flow Description, Structure of Data flow Description, Data type-vectors, Common VHDL programming Errors (Text 2, Chapter 2- 2.1- to- 2.4) L1, L2, L3

Module-4

Designing with programmable Logic Devices: Read only memories, Programmable Logic Arrays, Programmable Array Logic, Other sequential programmable Logic Devices (PLDs), Generics, Generate statements. (Text 1, Chapter 3- 3.1, 3.2, 3.3, 3.4) Design of Networks for Arithmetic Operations: Design of serial Adder with Accumulator, Design of Binary Multiplier, Multiplication of signed Binary Numbers, Design of Binary Divider (Text 1, Chapter 4- 4.1, 4.3, 4.4, 4.5) L1, L2, L3

Module-5

Synthesis: Highlights of synthesis, synthesis information from entity and module, Mapping process in the hardware domain- Mapping of signal assignment, variable L1, L2, L3 assignment, if statements, else-if statements, loop statement. (Text 2, Chapter5- 10.1, 10.2, 10.3) Hardware Testing and Design for Testability: Testing Combinational Logic, Testing Sequential Logic. (Text 1, Chapter 10- 10.1, 10.2))

Course Outcomes: After studying this course, students will be able to:

1. Understand the basic concepts of Digital Design
2. Implement various Combinational and sequential circuits using VHDL descriptions.
Write simple VHDL programs in different styles.
3. Design and verify the functionality of digital circuits (PLA, PAL, PLD) and Arithmetic
Operations.
4. Identify the suitable Abstraction level for a particular digital design.
5. Write the programs more effectively using Verilog tasks and directives. Perform timing and delay Simulation.
Students have to conduct the following experiments as a part of CIE marks along with other
Activities:
Conduct the following experiments using an suitable simulator and the required software tool.
1. Write a VHDL code to implement half and full adder using Data flow style.
2. Write a VHDL code to realize various logic gates.
3. Write a VHDL code to implement four-bit full adder using structural style.
4. Write a VHDL code to implement 2*2 unsigned combinational Array Multiplier.
5. Write a VHDL code to implement D Latch.
6. Implement JK flip flop modeling using VHDL process

Question paper pattern:

• Examination will be conducted for 100 marks with question paper containing 10 full
questions, each of 20 marks.
• Each full question can have a maximum of 4 sub questions.
• There will be 2 full questions from each module covering all the topics of the module.
• Students will have to answer 5 full questions, selecting one full question from each module.
• The total marks will be proportionally reduced to 60 marks as SEE marks is 60.

Text Books:

1. “Digital Systems Design using VHDL”, Charles H. Roth, Jr., The University of Texas at
Austin. 2006 reprint, Thomson Asia Pte Ltd, Singapore
2. “HDL Programming VHDL and Verilog”, Nazeih M. Botros, 2009 reprint, Dreamtech
press

Reference:

“VHDL for Programmable Logic”, Kevin Skahill, Pearson education, 2006