Digital System Design Using Verilog (21EC32)

Digital System Design Using Verilog

Course Code: 21EC32 
CIE Marks: 50
Teaching Hours/Week (L: T: P: S): (3:0:2:0) 
SEE Marks: 50
Total Hours of Pedagogy: 40 
hours Theory + 13 Lab slots 
Total Marks:100
Credits:04 
Exam Hours:03

Course objectives: This course will enable students to:

1. To impart the concepts of simplifying Boolean expression using K-map techniques and Quine- McCluskey minimization techniques.

2. To impart the concepts of designing and analyzing combinational logic circuits.

3. To impart design methods and analysis of sequential logic circuits.

4. To impart the concepts of Verilog HDL-data flow and behavioral models for the design of digital systems.

Module-1

Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey Minimization Technique. Quine-McCluskey using Don’t Care Terms. (Section 3.1 to 3.5 of Text 1).

Module-2

Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices (PLDs) (Section 5.1 to 5.7 of Text 2)

Module-3

Flip-Flops and its Applications: The Master-Slave Flip-flops (Pulse-Triggered flip-flops): SR flip-flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, JK, D and SR flip-flops. (Section 6.4, 6.6 to 6.9 (Excluding 6.9.3) of Text 2)

Module-4

Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description. (Section 1.1 to 1.6.2, 1.6.4 (only Verilog), 2 of Text 3) Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description. (Section 2.1 to 2.2 (only Verilog) of Text 3)

Module-5

Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1). (Section 3.1 to 3.4 (only Verilog) of Text 3) Verilog Structural description: Highlights of Structural description, Organization of structural description, Structural description of ripple carry adder. (Section 4.1 to 4.2 of Text 3)

PRACTICAL COMPONENT OF IPCC

Using suitable simulation software, demonstrate the operation of the following circuits:

Sl.No Experiments

1 To simplify the given Boolean expressions and realize using Verilog program.

2 To realize Adder/Subtractor (Full/half) circuits using Verilog data flow description.

3 To realize 4-bit ALU using Verilog program.

4 To realize the following Code converters using Verilog Behavioral description

a) Gray to binary and vice versa b) Binary to excess3 and vice versa

5 To realize using Verilog Behavioral description: 8:1 mux, 8:3 encoder, Priority encoder

6 To realize using Verilog Behavioral description: 1:8 Demux, 3:8 decoder, 2-bit Comparator

7 To realize using Verilog Behavioral description: Flip-flops: a) JK type b) SR type c) T type and d) D type

8 To realize Counters - up/down (BCD and binary) using Verilog Behavioral description. Demonstration Experiments (For CIE only – not to be included for SEE) Use FPGA/CPLD kits for downloading Verilog codes and check the output for interfacing experiments.

9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in the specified direction (by N steps).

10 Verilog programs to interface a Relay or ADC to the FPGA/CPLD and demonstrate its working.

11 Verilog programs to interface DAC to the FPGA/CPLD for Waveform generation.

12 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate its working.

Suggested Learning Resources:
Text Books

1. Digital Logic Applications and Design by John M Yarbrough, Thomson Learning, 2001.

2. Digital Principles and Design by Donald D Givone, McGraw Hill, 2002.

3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dreamtech press.

Reference Books:

1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning

2. Logic Design, by Sudhakar Samuel, Pearson/ Sanguine, 2007

3. Fundamentals of HDL, by Cyril P R, Pearson/Sanguine 2010

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Programming Assignments / Mini Projects can be given to improve programming skills.