Digital System Design using Verilog (BEC302)

Digital System Design using Verilog

Course Code BEC302 
CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2 
SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots 
Total Marks 100
Credits 04 
Exam Hours 03
Examination nature (SEE) Theory/Practical

MODULE-1 

Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, QuineMcCluskey Minimization Technique. Quine-McCluskey using Don’t CareTerms.(Section3.1to3.5ofText1). 

MODULE-2

Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs) (Section5.1to5.7 ofText2) 

MODULE-3

Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flipflops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, J K, D and SR flip-flops.(Section 6.4, 6.6 to 6.9 (Excluding 6.9.3)of Text2) 

MODULE-4

Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3) Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description.(Section2.1to2.2(only Verilog) of Text3) 

MODULE-5

Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1). (Section 3.1 to 3.4 (onlyVerilog)of Text 3) Verilog Structural description: Highlights of Structural description, Organization of structural description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)

Experiments 

1 To simplify the given Boolean expressions and realize using Verilog program 

2 To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description. 

3 To realize 4-bit ALU using Verilog program. 

4 To realize the following Code converters using Verilog Behavioral description a)Gray to binary and vice versa b)Binary to excess3 and vice versa 

5 To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder 

6 To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator 

7 To realize using Verilog Behavioral description: Flip-flops: a)JK type b)SR type c)T type and d)D type 

8 To realize Counters-up/down (BCD and binary)using Verilog Behavioral description. Demonstration Experiments (For CIE only–not to be included for SEE) Use FPGA/CPLD kits for down loading Verilog codes and check the output for interfacing experiments. 

9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in the specified direction (by N steps). 

10 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate its working. 

Suggested Learning Resources: Books 

1. Digital Logic Applications and Design by John MYarbrough,Thomson Learning,2001. 

2. Digital Principles and Design by Donald DGivone,McGrawHill, 2002. 3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dream techpress. 

ReferenceBooks: 

1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning 

2. Logic Design, by Sudhakar Samuel, Pearson/Sanguine, 2007 

3. Fundamentals of HDL,by Cyril PR, Pearson/Sanguine2010