BASICS OF –VHDL LAB
Course Code BEEL456A
CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2:0
SEE Marks 50
Credits 01
Exam Hours 03
Examination nature (SEE) Practical/Viva-Voce
Experiments
Note:
Programming can be done using any compiler. Download the programs on a FPGA/CPLD board and
performance testing may be done using 32 channel pattern generator and logic analyser, apart from
verification by simulation with tools such as Altera/Modelsim or equivalent
1 Write Verilog program for the following combinational design along with test bench to verify
the design:
a) 2 to 4 decoder realization using NAND gates only (structural model)
b) 8 to 3 encoder with priority encoder and without priority encoder (behavioral model)
c) 8 to 1 Multiplexer using case statement and if statement
d) 4 bit binary to gray code converter using 1 bit gray to binary converter 1 bit adder and
subtractor.
2 Model in Verilog for a full adder and add functionality to perform logical operations of XOR,
XNOR, AND and OR gates. Write test bench with appropriate input patterns to verify the
modelled behavior.
3 Verilog 32 bit ALU shown in figure below and verify the functionality of ALU by selecting
appropriate test patterns. The functionality of the ALU is shown in Table-1.
a) Write test bench to verify the functionality of the ALU considering all possible input
patterns
b) The enable signal will set the output to required functions if enabled, if disabled all the
outputs are set to tri-state.
c) The acknowledge signal is set high after every operation is complete.
4 Write Verilog code for SR, D and JK and verify the flip flop
5 Write Verilog code for 4 bit BCD synchronous counter
6 Write Verilog code for counter with given input clock and check whether it works as clock
divider performing division of clock by 2, 4, 8 and 16 . Verify the functionality of the code.
PART B
Note;
Interfacing and Debugging:
(ED) WinXp, PSpice, MultiSim, Proteus, CircuitLab, or any other equivalent tool can
be used.
Demonstration Experiments ( For CIE )
7 Write a Verilog code to design a clock divider circuit that generates ½, 1/3rd, 1/4th ,clock from
given input clock . Port the design to FPGA and validate the functionality through CRO.
8 Interface a DC motor to FPGA and write Verilog code to change its speed and direction
9 Interface a stepper motor to FPGA and write Verilog code to control the stepper motor rotation
which in turn may control a Robatic arm. External switches to be used for different controls
like rotate the stepper motor:
a)+ N steps if the switch number 1 of a DIP switch is closed.
b)+N/2 steps if switch number 2 of a DIP switch is closed.
c)-N steps if switch number 3 of a DIP switch is closed etc.
10 Interface a DAC to FPGA and write Verilog code to generate a sine wave of frequency f KHz, ex f
= 100 KHz, or 200 KHz etc, . Modify the code to down sample the frequency to f/2 KHz.
Display the original and down sampled signals by connecting them to CRO.
11 Write Verilog code using FSM to simulate elevator operation.
12 Write Verilog code to convert an analog input signal of a sensor to digital form and to display
the same on a suitable display like simple set of LEDs , 7 segment display digits or LCD display
Suggested Learning Resources:
HDL Programming fundamentals , VHDL and Verilog, N. Botros, Cengage Learning,
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