Digital System Design Using Verilog (1BEC302)

Digital System Design Using Verilog

Course Code 1BEC302 
Scheme 2025
Type of course IPCC 
Semester III
Teaching Hours/Week (L:T:P) 3:0:2 
CIE Marks 50
Total Hours of Pedagogy (L:T:P:SL&TW) 42:0:28:50:0 
SEE Marks 50
Credits 4 
Total Marks 100
Type of Examination (IPCC): Theory- CIE +SEE, Lab- CIE only. 
Exam Hours 3

Module-1

Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, Quine McCluskey Minimization Technique. QuineMcCluskey using Don’t Care Terms.

Text book 1: Section 3.1 to 3.5

Module-2

Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors, Decimal Adders, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices (PLDs)

Text book 2: Section 5.1 to 5.7

Module-3

Introduction to Verilog: Structure of Verilog module, Styles of Description, Ports, Operators, Data Types,

Text book 3: Section 1.1 to 1.6.2 (only Verilog)

Verilog Data flow description: Highlights of Data flow description, Signal Declaration and Assignment Statement, Structure of Data flow description.

Text book 3: Section 2.1 to 2.2 (only Verilog)

Module-4

Flip-Flops and its Applications: The Master-Slave Flip-flops (Pulse-Triggered flip-flops): The basic bistable element, Latches, Timing Considerations, SR flip flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, J K, D and SR flip-flops.

Text book 2: Section 6.1 to 6.4, 6.6 to 6.9 (Excluding 6.9.3).

Module-5

Verilog Behavioral Description: Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers.

Text book 3: Section 3.1 to 3.4 (only Verilog)

Verilog Structural Description: Highlights of Structural description, Organization of structural description, Structural description of ripple carry adder.

PRACTICAL COMPONENTS OF IPCC

1. Boolean Expression Simplification and Logic Circuit Implementation

 a) Simplify the given Boolean expression.

 b) Design a Full Adder.

 Realize the corresponding circuits using a breadboard or digital trainer kit and verify their operation.

2. Adder/Subtractor Circuits Using Verilog Dataflow Description

 a) Realize a Half Adder.

 b) Realize a Full Adder.

 c) Realize a Half Subtractor.

 d) Realize a Full Subtractor.

Implement the circuits using Verilog dataflow description. Simulate the designs and test them on an FPGA board.

3. 4-bit ALU Using Verilog

Write Verilog code for a 4-bit Arithmetic Logic Unit (ALU). Simulate the design and test it on an FPGA board.

4. Code Converters Using Verilog Behavioral Description

Write Verilog code for the following code converters using behavioral description. Simulate the designs and test them on an FPGA board.

 a) Gray-to-Binary and Binary-to-Gray

 b) Binary-to-Excess-3 and Excess-3-to-Binary

5. Multiplexer, Decoder and Encoder Using Verilog

 Realize the following using Verilog behavioral description. Simulate the designs and test them on an FPGA board:

 a) 8:1 Multiplexer

 b) 3:8 Decoder

 c) 8:3 Priority Encoder

6. BCD-to-7-Segment Display and Switch/LED Interfacing Using Verilog

 a) Write a Verilog program to design a BCD-to-7-segment display decoder.

 b) Write a Verilog program to interface switches and LEDs with an FPGA/CPLD and demonstrate their operation.

 Simulate the designs and test them on an FPGA board.

7. Demultiplexer and Comparators Using Verilog

Realize the following using Verilog behavioral description. Simulate the designs and test them on an FPGA board:

 a) 1:8 Demultiplexer

 b) 2-bit Comparator

 c) 4-bit Magnitude Comparator

8. Flip-Flops Using Verilog

Realize the following flip-flops using Verilog behavioral description. Simulate the designs and test them on an FPGA board:

 a) JK Flip-Flop

 b) SR Flip-Flop

 c) T Flip-Flop

 d) D Flip-Flop

9. Up/Down Counters Using Verilog Structural Description

 Design and implement BCD and binary up/down counters using Verilog structural description. Simulate the designs and test them on an FPGA board.

10. Stepper Motor Interfacing Using Verilog

 Write a Verilog program to interface a stepper motor with an FPGA/CPLD through a suitable motor driver circuit and rotate the motor in the specified direction by a specified number of steps.

11. FSM-Based Sequence Detector Using Verilog

 Design a Finite State Machine (FSM) to detect a given sequence, such as 1010. The input shall be applied serially, and the output shall go HIGH whenever the sequence is detected. The design shall support overlapping sequences. Write the Verilog code, simulate the design using a testbench, and test it on an FPGA board.

12. Sequential Circuit Design Using Flip-Flops

 Design a specified sequential circuit using flip-flops, write the corresponding Verilog code, simulate the design using a testbench, and test it on an FPGA board.

Note: Experiment 1 focuses on hardware-based logic circuit realization using a breadboard or digital trainer kit. Experiments 2–12 cover combinational circuits, code converters, sequential circuits, counters, FPGA interfacing, display interfacing, motor interfacing, and FSM design using Verilog HDL.

Suggested Learning Resources: 

Text books:

1. J. M. Yarbrough, Digital Logic Applications and Design. Clifton Park, NY, USA: Thomson Learning, 2006.

2. D. D. Givone, Digital Principles and Design. New York, NY, USA: McGraw-Hill, 2002.

3. N. Botros, HDL with Digital Design: VHDL and Verilog. Dulles, VA, USA: Mercury Learning and Information, 2015

Reference books / Manuals:

1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning

2. Fundamentals of HDL, by Cyril PR, Pearson/Sanguine 2010

3. Logic Design, by Sudhakar Samuel, Pearson/Sanguine, 2007